Device Layout and Simulation Engineer

Job Description

Job Title: Device Layout and Simulation Engineer, Quantum AI. Location: Goleta, CA, USA / Mountain View, CA, USA

Responsibilities:

• Build, maintain, and streamline infrastructure for quantum processor and associated device layout and simulation workflows.
• Support frontend and backend infrastructure and custom toolkits used for quantum processor designs and associated analog, DC, and RF devices.
• Develop and maintain custom programmatic CAD layout tools, graphical layout tools, and Finite Element Simulation workflows.
• Work with tools such as KLayout and various Finite Element Simulation platforms for physical device simulations;
• Develop, maintain, and improve end-to-end layout, simulation, and verification infrastructure used by designers across Quantum AI.
• Work on longer-term projects to streamline workflows for non-standard devices and quantum packaging simulations.
• Collaborate with designers across multiple teams to support the release and deployment of layout and simulation software upgrades.
• Maintain and expand technical documentation covering layout, simulation, and integrations with other teams.
• Work efficiently in an agile research environment and adapt to changing requirements in quantum device design and modeling.
• Help improve the quantum processor production cycle through more efficient device layout and simulation infrastructure.

Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized technical field such as Optics, Sensors, or Audio/DSP, or equivalent practical experience.
• At least 3 years of experience with Python or other programming languages;
• At least 3 years of experience with electromagnetic simulations and Finite Element Simulation tools such as Ansys HFSS or COMSOL.
• Experience with Git version control.

Preferred:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
• Experience with custom programmatic CAD layout and verification tools.
• Knowledge of FEM macro development techniques.
• Experience with caching and massive parallelization techniques;
• Familiarity with superconducting circuit architectures and quantum computing.
• Familiarity with integrated circuit fabrication techniques and processes.

Benefits and Compensation:

• Salary range: $132,000 to $189,000 per year.
• Target bonus: 15%.
• Equity and additional benefits.
• Google provides a comprehensive employee benefits program;
• Opportunities to work on Google's large-scale quantum computing initiative and quantum processor development.
• Individual compensation is determined based on job-related skills, experience, education, and training.

Other Information:

• The position allows candidates to indicate a preferred working location between Goleta, California, and Mountain View, California.
• English proficiency is required for this role to facilitate effective global collaboration and communication.
• Google is an equal opportunity and affirmative action employer;
• Google does not accept agency resumes for this position.