Analog / Mixed-Signal IC Design Engineer

Job Description

Job Title: Senior Analog / Mixed-Signal IC Design Engineer. Location: Palo Alto, California, United States

Responsibilities:

• Design and develop high-performance analog and mixed-signal integrated circuit blocks, including:
  • Data converters such as ADCs and DACs
  • Amplifiers such as LNAs, TIAs, and op-amps
  • Bandgap references
  • Biasing circuits
  • Regulators
• Define system architectures and make design trade-offs involving noise, linearity, power, area, and bandwidth.
• Perform transistor-level circuit design, simulation, and optimization using industry-standard tools.
• Develop behavioral models using Verilog-A and SystemVerilog real-number modeling (RNM) for system-level verification and architectural exploration.
• Work closely with layout engineers to maintain circuit performance through parasitic-aware design and careful floorplanning.
• Perform post-layout simulations and sign-off analyses, including PVT, Monte Carlo, and corner analysis;
• Collaborate with digital and verification teams to achieve robust mixed-signal integration.
• Lead or manage silicon bring-up, debugging, and laboratory characterization.
• Prepare clear design documentation and participate in design reviews.
• Take ownership of assigned deliverables and drive projects through completion, including under tight timelines.
• Contribute across disciplines when needed, including areas outside the primary specialization;
• Maintain organized workflows for simulations, design iterations, and analysis results.

Qualifications:

• Master’s or PhD degree in Electrical Engineering or a related field.
• Strong fundamentals in analog circuit design and device physics.
• Proven experience designing and taping out analog or mixed-signal integrated circuits.
• Expertise in CMOS or SiGe design across one or more process nodes.
• Proficiency with SPICE-based simulation tools such as Spectre and HSPICE;
• Deep understanding of noise, mismatch, stability, and nonlinearity.
• Ability to design from first principles and solve complex circuit problems creatively.
• Strong organizational skills for managing large design spaces involving corners, Monte Carlo simulations, and design trade-offs.
• Demonstrated ownership and commitment to delivering high-quality results.

Preferred:

• Experience with data converters, RF/analog front-ends, or high-speed interfaces.
• Experience with mature and advanced semiconductor process nodes. FinFET or more advanced technologies are a plus.
• Hands-on experience with silicon validation and laboratory debugging.
• Experience contributing across complete chip development cycles.
• Experience with the Cadence Virtuoso design environment;
• Hands-on experience with layout, tapeout, and bench validation.
• Familiarity with SystemVerilog RNM and/or Verilog-A modeling.

Benefits and Compensation:

The estimated annual base salary ranges are based on the geographic zone where the position is filled:

• Zone 1, Bay Area and NYC: $167,800 to $197,200 USD
• Zone 2, including Los Angeles and Washington, DC: $151,100 to $177,500 USD
• Zone 3, including Austin, Chicago, and Sacramento: $134,300 to $157,800 USD
• Zone 4, including Nashville, Phoenix/Tempe, and many remote locations: $117,500 to $138,000 USD

Actual compensation may vary depending on qualifications, education, training, competencies, experience, geographic location, business needs, and internal equity.

Full-time employees are eligible for:

• Competitive health coverage for employees and dependents.
• 401(k) with company match.
• Equity grants.
• Financial wellness tools and planning resources.
• Wellness benefits.
• Family support programs;
• Life and disability insurance.
• Paid leave programs.
• Company-designated paid holidays.
• Discretionary time off (DTO).
• End-of-year company shutdown.

Some benefits have eligibility requirements and may vary by location, role, or employment status. Many benefits are subsidized or fully paid by the company.