Quantum Design Enablement Engineer

Job Description

Job Title: Quantum Design Enablement Engineer. Location: College Park, Maryland, USA

Job Type: Full-Time (Hybrid/On-site)

Responsibilities:

• Serve as the primary technical contact for external foundry partners.

• Work with foundries to define, implement, and troubleshoot Process Design Kits (PDKs).

• Ensure PDKs accurately reflect foundry capabilities, manufacturing processes, and design limitations.

• Manage the complete tapeout process.

• Perform mask layout validation and physical verification, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS).

• Ensure final GDSII/OASIS files meet foundry requirements before manufacturing handoff;

• Work closely with manufacturing and product design teams to communicate foundry requirements and process updates.

• Translate manufacturing requirements into clear design rules and best practices for design engineers.

• Perform layout modifications, frame generation, and reticle assembly to prepare masks for manufacturing.

• Create custom layouts for test structures, process monitors, and simple test chips when required.

• Use foundry-provided DRC/LVS rule decks and develop custom internal rule checks for specialized trapped-ion quantum computer designs.

• Analyze tapeout data and foundry feedback to identify opportunities for improvement.

• Improve PDKs, design rules, and design-to-manufacturing workflows.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Physics, Materials Science, or a related technical field.

• 3–5 years of industry experience in semiconductor manufacturing, design enablement, tapeout operations, or a closely related field.

• Hands-on experience with physical verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys IC Validator.

• Experience performing standard DRC, LVS, and ERC checks.

• Proficiency with layout and viewing tools such as Cadence Virtuoso or KLayout;

• Ability to perform layout modifications and detailed mask reviews.

• Strong understanding of PDK architecture, technology files, and foundry design rules.

• Excellent communication skills, with the ability to coordinate technical requirements between foundry engineers and internal design teams.

Preferred:

• Strong Python programming skills.

• Experience with Python-based layout generation frameworks such as gdsfactory, gdspy, or KLayout.

• Experience using Git for version control.

• Familiarity with specialized semiconductor and microfabrication technologies, including integrated photonics, MEMS, or specialized BEOL metallization.

• Experience writing or modifying physical verification rules, such as Calibre SVRF/TVF or equivalent.

• Familiarity with CMOS device modeling principles and compact modeling methods.

• Understanding of Parasitic Extraction (PEX) processes and tools.

• Knowledge of how physical layouts affect parasitic capacitance, RF performance, and device behavior.

Benefits and Compensation:

• Base salary range: $126,887–$166,127 per year.

• Total compensation includes base salary, bonus, and equity.

• Comprehensive medical, dental, and vision insurance.

• 401(k) matching.

• Unlimited paid time off (PTO).

• Paid holidays.

• Parental and adoption leave.

• Legal insurance.

• Home technology stipend.

Note: IonQ also lists a wage transparency range of $124,000–$186,000. Actual compensation depends on qualifications, experience, education, location, and internal compensation considerations.

Application Information:

Candidates can apply through IonQ's official careers website. The application requires contact information, a resume/CV, LinkedIn profile, work authorization details, and consent to the applicant privacy and background screening policies.