Silicon Engineer, Digital Design

Job Description

Job Title: Silicon Engineer, Digital Design, Quantum AI. Location: Mountain View, CA or Goleta, CA (candidate can share preferred location)

As a Silicon Engineer in Digital Design, you will contribute to building advanced ASICs for the control and readout of large-scale quantum processors; This role involves collaboration with digital, verification, physical design, and mixed-signal engineers, as well as researchers in quantum computing; Your work will shape microarchitectures that support high-performance, error-corrected quantum systems.

Responsibilities:

• Own the development of RTL-based silicon designs for quantum processors.
• Collaborate with quantum researchers, hardware engineers, and system architects to translate requirements into efficient microarchitectures.
• Participate in architectural design and contribute to high-quality technical documentation.
• Develop and implement block-level and chip-level RTL (including Lint/CDC/FV/UPF checks).
• Engage in verification, debug, simulation, and test planning to ensure robust, bug-free designs.
• Work on synthesis, timing/power closure, and silicon bring-up;
• Evaluate, select, and integrate third-party IPs for quantum control processors.
• Partner with external ASIC service providers to ensure timely, high-quality product delivery.
• Contribute to planning and execution of post-silicon testing.

Qualifications:

• Bachelor’s degree in Electrical Engineering or related technical field.
• 5 years of experience with digital logic design and RTL design concepts.
• 5 years of experience in IP development or IP integration.

Preferred:

• 8 years of experience with digital logic design, RTL concepts, Verilog, or SystemVerilog.
• Experience in building digital control and signal processing chains for mixed-signal sensing or actuation ASICs.
• Knowledge of ASIC design methodologies (clock domain checks, reset checks, low power design);
• Experience collaborating across system architecture, verification, physical design, and software teams for ASIC development.
• Expertise in at least one of the following: CPU Processor Cores, Buses/Fabric/Network-on-Chip, Debug/Trace, Interrupts, Clocks/Reset.

Compensation and Benefits:

• US base salary range: $156,000–$229,000 (depending on location, experience, and skills).
• Additional benefits include bonus, equity, healthcare, and other employee benefits;
• Learn more about Google’s benefits package during the hiring process.

Equal Opportunity Statement: Google is an equal opportunity employer committed to diversity, equity, and inclusion; All qualified applicants will receive consideration without regard to race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected status.