Photonic Layout Design Engineer

Job Description

Job Title: Senior Photonic Layout Design Engineer. Location: Santa Clara, CA, USA

Responsibilities:

• Collaborate with photonics, CMOS, electronics, and systems engineers on chip-level layout and verification.
• Lead chip floorplanning, waveguide routing, and photonic chip assembly for multiple concurrent projects.
• Execute custom layout for mixed-signal blocks (PLLs, high-speed I/O, ESD structures) using Cadence Virtuoso.
• Perform DRC/LVS verification and interface with foundries using tools like Calibre, Dracula, or Hercules;
• Support post-processing tasks including fill insertion, DRC mitigation, and chip sign-off;
• Adapt layouts for integration with silicon photonic and SERDES components;

Qualifications:

• BS in Electrical Engineering or related field.
• 5+ years of hands-on analog or mixed-signal layout design experience.
• Deep knowledge of CMOS technologies and silicon photonic design concepts.
• Proficiency with Cadence custom layout tools and verification flows (DRC/LVS);
• Familiarity with scripting languages (Python, Perl, SKILL) for layout automation and verification;
• Strong teamwork and communication skills.

Preferred:

• Silicon Photonic integration background.
• Experience working across multiple disciplines and managing foundry interactions.

Benefits:

• Competitive base salary range: $104,000 – $230,000 (based on experience and location).
• Equity compensation and comprehensive benefits package;
• Continuous learning opportunities in a cutting-edge technology environment;