Silicon Engineer, Design Verification

Job Description

Job Title: Silicon Engineer, Design Verification, Quantum AI. Location: Mountain View, CA or Goleta, CA (candidate can express location preference.

Your work will involve planning and executing full lifecycle verification of ASICs, working closely with architects, digital designers, and external IP vendors; You will build test environments using SystemVerilog and UVM, create verification plans, and ensure full coverage and integration of internal and external components.

Responsibilities:

• Plan the verification strategy for complex digital blocks based on design specifications.
• Collaborate with design teams to identify and simulate key scenarios.
• Develop and maintain SystemVerilog/UVM environments;
• Write and run verification test cases, debug failures, and analyze results.
• Track and close coverage metrics to ensure all parts of the chip are tested before tape-out.
• Integrate Verification IP from third-party vendors into Google's DV flow.

Qualifications:

• Bachelor’s degree in Electrical Engineering or a related field, or equivalent experience.
• At least 5 years of experience in digital design verification.
• Hands-on experience with SystemVerilog/UVM;
• Experience verifying SoCs with CPUs, peripherals, and bus interfaces.
• Proficiency in scripting languages like Python or Perl.

Preferred:

• Experience with DV for mixed-signal ASICs, including analog and RF components.
• Background in setting up UVM environments and coverage-driven verification.
• Familiarity with processors such as ARM or RISC-V;
• Knowledge of formal verification tools like JasperGold or Questa Formal.
• Strong grasp of digital logic and architecture principles.

Compensation and Benefits:

• Competitive salary plus performance-based bonus and equity.
• Full health, dental, and vision coverage;
• Additional perks and support available through Google’s benefits program.